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Example 16.7 (Complete VHDL code available.) Generate the VHDL model of a generic oating-point adder-subtractor. It is made up of four blocks:

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Other chapters discuss the hazards involved with mixing clock and reset types in procedural descriptions, but if any given module has only one clock and reset, these problems are less likely to arise. 12.3.1.3 Multiple Instantiations

1. Alignment (Figure 16.1):

To assist in the development of your proposal, we have provided the following data:

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If there are cases where certain logic operations occur more than once in a particular module (or across multiple modules), a natural partition to the design would be to group that block into a separate module and push it into the hierarchy for multiple instantiations. There are a number of advantages to the partitioning described in Figure 12.14. First of all, it will be much easier to assign blocks of functionality to designers independent of one another. One designer can focus on the top-level design, organization, and simulation, while another designer can focus on the functionality speci c to the submodule. If the interfaces are clearly de ned, this type of group design can work very well. If, however, both designers are developing within the same module, greater confusion and dif culty can occur. Additionally, the submodules can be reused in other areas of the design or perhaps in different designs altogether. It is typically much easier to reinstantiate an existing module rather than cut and paste out of larger modules and redesign the corresponding interfaces. One dif culty that may arise with such a strategy is the case where there are slight variations on the individual modules such as data width, iteration count, and so forth. These cases are addressed with a design method called parameterization, whereby like-kind modules can share a common code-base that is parameterizable on an instance-by-instance basis. The next section discusses this in more detail.

entity alignment is port ( sign1, sign2, operation: in std_logic; e1, e2: in integer; s1, s2: in digit_vector(0 downto -p); dif: inout natural; sign, new_sign2: out std_logic; e: out natural; aligned_s1, aligned_s2: out digit_vector(0 downto -(p+3)) ); end alignment; architecture behavior of alignment is signal actual_sign2: std_logic; signal s, new_s2: digit_vector(0 downto -p); signal shift_length: natural; signal sticky: digit; begin actual_sign2<=operation xor sign2; swap: process(sign1, actual_sign2, e1, e2, s1, s2, s) begin if e1<e2 then dif<=e2-e1; e<=e2; sign<=actual_sign2; new_sign2<=sign1; s<=s2; new_s2<=s1; else dif<=e1 - e2; e<=e1; sign<=sign1; new_sign2<=actual_sign2; s<=s1; new_s2<=s2; end if; aligned_s1(-(p+1))<=0; aligned_s1(-(p+2))<=0; aligned_s1(-(p+3))<=0; for i in 0 downto -p loop aligned_s1(i)<=s(i); end loop;

a digital design: area. Here we also discuss methods for architectural area optimization in an FPGA. We will discuss area reduction based on choosing the correct topology. Topology refers to the higher-level organization of the design and is not device speci c. Circuit-level reduction as performed by the synthesis and layout tools refers to the minimization of the number of gates in a subset of the design and may be device speci c. A topology that targets area is one that reuses the logic resources to the greatest extent possible, often at the expense of throughput (speed). Very often this requires a recursive data ow, where the output of one stage is fed back to the input for similar processing. This can be a simple loop that ows naturally with the algorithm or it may be that the logic reuse is complex and requires special controls. This section describes both techniques and describes the necessary consequences in terms of performance penalties. During the course of this chapter, we will discuss the following topics in detail:

Description Distribution of active employees by location Assets by fund Trust Statement as of December 31, 2004 COMPANY ABC SPD and plan amendments COMPANY ABC plan document Copy of most recent 5500 Most recent ADP/ACP testing results Comments Included within this document Included within this document Electronic attachment Electronic attachment Electronic attachment Available upon request Passed; available upon request

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