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The CPU is then free to continue computing while the data are moved in or out This is a further improvement in system efficiency, and today DMA is almost universally used for disk and other block transfers SUMMARY Modern computers implement the von Neumann architecture, or stored program computer design Program instructions and data are both stored in main memory The components of the computer design are the CPU (including the control unit and the ALU), memory, and input/output Computers operate in base-2 arithmetic Any number base can be used for computation and, just as humans find 10 fingers a convenient basis for computation, machine builders find 2-state (on off) devices easy to build and convenient for computation We discussed the simple math facts for binary math, and showed how subtraction is accomplished using 2 s-complement addition.

A plot of Mdb is displayed in Fig. 9-8(b). The curve is essentially at below ! 0:1=RC; thus, all frequencies below 0.1=RC are passed with the dc gain R=R1 . A 3-db reduction in gain is experienced at the corner frequency 1= 1=RC, and the gain is attenuated by 20 db per decade of frequency change for frequencies greater than 10=RC.

CHAP. 13]

Fig. 4-4

7 8 9 10 11 12 13

We also discussed the concept of the computer word, and the implications of computer word sizes of different numbers of bits Data are encoded in different ways, depending on the type of data We described integer, floating-point and character encodings The program interprets the bit pattern in a computer word depending on what it expects to find in that memory location The same bit pattern can be interpreted in different ways when the program expects one data type or another The programmer is responsible for insuring that the program correctly accesses its data The CPU consists of two parts The control unit is responsible for implementing the steady cycle of retrieving the next instruction, decoding the bit pattern in the instruction word, and executing the instruction..

The commonly used voltage-divider bias arrangement of Fig. 4-5(a) can be reduced to its equivalent in Fig. 4-5(b), where the Thevenin parameters are given by RG R1 R2 R1 R2 and VGG R1 V R1 R2 DD 4:3

pq.add("IT"); pq.add("ES"); while (!pq.isEmpty()) { System.out.printf("%s } } }

+ R1 S + RS CS _

", pq.remove());

The arithmetic and logic unit (ALU) is responsible for performing mathematical, logical, and comparison functions The instruction set of a computer is the list of primitive operations that the computer hardware is wired to perform Modern computers have between 50 and 200 machine instructions, and instructions fall into the categories of data movement, arithmetic operations, logical operations, control transfer, I/O, and comparisons Most programmers today write in higher-level languages, and so are isolated from direct experience of the machine instruction set, but at the hardware level, the machine instruction set defines the capability of the computer Main memory provides random access to data and instructions Today all manufacturers measure memory with a count of 8-bit bytes Most machines, regardless of 16-bit, 32-bit, or 64-bit word size, also offer byte addressability.

0 (a) (b)

The output is:

Fig. 4-5

With iG 0, application of KVL around the gate-source loop of Fig. 4-5(b) yields the equation of the transfer bias line, iD VGG vGS RS RS 4:4

The collection pq is a priority queue, so its elements are removed according to their priorities. The element type for this queue is String, which has its own natural ordering: alphabetical order. So regardless of the order in which they are inserted, they are removed in alphabetical order.

Since access to memory takes longer than access to registers on the CPU itself, modern designs incorporate cache memory near the CPU to provide a copy of the contents of a section of main memory in order to obviate the need to read from main memory so frequently Cache memory entails complexity to manage cache coherency, but it typically results in speedup of average memory access time by 50 percent Input and output functions today are based on I/O controllers, which are small special-purpose computers built to control the details of the I/O device, and provide a local memory buffer for the information being transferred in or out Computers today use an interrupt system to allow the CPU to process other work while I/O occurs under the supervision of the I/O controller When the transfer is complete, the I/O controller notifies the CPU by generating an interrupt.

which can be solved simultaneously with (4.2) or plotted as indicated on Fig. 4-2(b) to yield IDQ and VGSQ , two of the necessary three quiescent variables. Application of KVL around the drain-source loop of Fig. 4-5(b) leads to the equation of the dc load line, iD VDD vDS RS RD RS RD 4:5

If the element type has no natural ordering, then PriorityQueue instances will apply the compareTo() method to determine priorities among the elements. EXAMPLE 13.7 Using Elements that Explicitly Implement the Comparable Interface

which, when plotted on the drain characteristics of Fig. 4-2(a), yields the remaining quiescent value, VDSQ . Alternatively, with IDQ already determined, VDSQ VDD RS RD IDQ